Session 14 overview: Digital clocking and PLLs: High-performance digital subcommittee

摘要

Many analog components are now leveraging digital technology. PLLs are increasingly integrating digital techniques and building blocks and are being built directly on digital SoCs. This integration continues to reduce power and cost in systems. This session begins with four papers on digital PLLs that showcase new design techniques. This includes an MDLL with a 400fs jitter and a PLL using cutting-edge 22nm process technology. We also have an innovative PLL that advances critical figures-of-merit through the use of digital techniques.