A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme

机译：一个4-Mb MRAM宏，包括共享的写选择晶体管单元并使用泄漏复制读取方案

获取原文

页面导航

摘要
著录项
引文网络
相似文献
相关主题

摘要

We propose an MRAM macro architecture for SoCs to reduce their area size. The .shared write-selection transistor (SWST) architecture is based on 2T1MTJ MRAM cell technology'', which enables the same fast access time as and with smaller cell area than that

机译：我们为SoC提出了MRAM宏架构，以减小其面积。共享写选择晶体管（SWST）架构基于2T1MTJ MRAM单元技术''，该技术实现了与2T1MTJ MRAM单元技术相同的快速访问时间，并具有比其更小的单元面积

著录项

来源
《Solid-State Circuits Conference, 2007 IEEE Asian》|2007年|P.220-223|共4页
会议地点 Jeju CityKorea (South)
作者
Nebashi; R.; Sakimura; N.; Sugibayashi; T.; Kasai; N.;
展开▼
作者单位

展开▼
会议组织
原文格式 PDF
正文语种
中图分类
关键词
CMOS memory circuits; random-access storage; system-on-chip; 2T1MTJ cell technology; 81T64MTJ cell array; CMOS process; MRAM macro architecture; SPICE simulation; SoC; leakage-replication read scheme; macro cell array; magnetic random access memory; shared write-sel;

机译：CMOS存储电路；随机存取存储；片上系统； 2T1MTJ电池技术； 81T64MTJ细胞阵列; CMOS工艺； MRAM宏架构； SPICE仿真； SoC;泄漏复制读取方案；宏单元阵列；磁性随机存取存储器；共享写;

相似文献

外文文献
中文文献
专利

1. Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros [J] . Ryusuke NEBASHI, Noboru SAKIMURA, Tadahiko SUGIBAYASHI, IEICE Transactions on Electronics . 2009,第e92acn4期

机译：大容量MRAM宏的共享写选择晶体管单元和泄漏复制读取方案
2. A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes [J] . Chang M.-F., Sheu S.-S., Lin K.-F., Solid-State Circuits, IEEE Journal of . 2013,第3期

机译：高速7.2ns读写随机存取4-Mb嵌入式电阻式RAM（ReRAM）宏，使用耐工艺变化的电流模式读取方案
3. Quasi-worst-condition built-in-self-test scheme for a 4-Mb loadless CMOS four-transistor SRAM macro [J] . Koichi Takeda, Yoshiharu Aimoto, Kazuyuki Nakamura, 電子情報通信学会技術研究報告. 電子部品·材料. Component Parts and Materials . 2001,第517期

机译：4 Mb无负载CMOS四晶体管SRAM宏的准最坏条件内置自检方案
4. A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme [C] . Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, IEEE Asian Solid-State Circuits Conference . 2007

机译：一个4 MB MRAM宏，包括共享写入晶体管单元并使用泄漏复制读取方案
5. A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells [O] . DATTA A, ASNANI R, MAHAPATRA S 2009

机译：一种新颖的门控反向读取方案，可控制深层拆分门SONOS闪存EEPROM单元中多位/单元操作的位耦合和读干扰

A 4-Mb MRAM macro comprising shared write-selection transistor cells and using a leakage-replication read scheme

摘要

著录项

引文网络

相似文献

相关主题

期刊订阅