FPGA Implementation of Full Parallel LDPC Encoder

摘要

This paper gives a detailed introduction to the FPGA implementation of Full Parallel Low-Density Paritv-Check(LDPC) Encoder, which is designed base on Richardson-Urbanke Algorithm with a code length 4096. code rate 4/5 on CCSDS standard. The proposed design use LUTs to solve matrix multiplication with low-complexity, the encode result can output in 4 clocks, the speed of the encoder can be higher than 6.4 Gbps, and the resource utilization is acceptable.