Parallel Test Implementation of Devices That Need Matching Loop with One Sequencer

摘要

Testing of many of today's devices, such as MCUs, requires synchronization of input signals with their internal signals before the actual testing task can be performed. The synchronization of these signals can be verified by checking the status of the output pins. The common testing technique used to insure that the device is in such a synchronization state is matching loop. Matching for a single site is easy. But the drive to lower the cost of test has made parallel test development essential. To achieve parallel test and improve test economics, changes in both test hardware design and test software development are required. The real story of providing a lower cost of test solution by testing 4-sites in parallel of the ciu9108, a smart card ASIC, is addressed in this paper. We will explain how to implement parallel testing on devices which need to perform matching loop, using a tester with only one sequencer.