REDUCTION OF THE BASE-COLLECTOR CAPACITANCE OF HETEROSTRUCTURE BIPOLAR TRANSISTORS USING REGROWTH OVER A PATTERNED SUBCOLLECTOR

摘要

Here we report on the use of regrowth over a patterned subcollector to achieve a reduction in the base-collector capacitance, C_(BC), for InP/InGaAs latticed matched to InP based HBT devices. After patterning the sub-collector, an initial MOCVD regrowth is done followed by MOMBE regrowth of the remainder of the structure. All of the lithography was done using a stepper. We have developed a process to protect the initial alignment features during the regrowth steps to ensure proper realignment. This is a critical issue particularly for the smaller devices where the regrowth technique can have an advantage. Results for devices with a 2X8 urn~2 emitter strip gave maximum f_T and f_(max) values of 105GHz and 130GHz, respectively. These values were limited by a somewhat high collector resistance due to an etching problem near the subcollector which increased the contact resistance. More importantly C _(BC) values of 12.5fF and 9fF for a 2X8um~2 device were extracted from the s-parameter data at I_c = 2mA and 9.5mA, respectively. This seems to indicate that only the area where the initial subcollector was defined contributed to C_(BC). In the layout of the device the actual base area is > l00um~2 which would give about 33fF assuming 0.33fF/um~2 for a 300nm collector thickness. The measured values were closer with to actual patterned subcollector area of about 30um~2.