An IF digitizer IC employing a continuous-time bandpass delta-sigma ADC

摘要

A 65-nm CMOS IC containing a synthesizer, a continuous-time bandpass delta-sigma ADC and associated digital filter digitizes 200–400 MHz inputs with bandwidths up to 100 MHz. With the ADC clock supplied by the internal synthesizer, the observed phase noise on a 430-MHz carrier is −137 dBc/Hz at 750-kHz offset. The gain of the IC is adjustable over a 39-dB range using an LNA in parallel with a resistive attenuator. The IC achieves NF = 7.5/26 dB and IIP3 = 8/36 dBm at the −12-dB gain settings. The ADC''s continuous-time architecture provides inherent alias protection, with ∼70 dB of alias attenuation observed in practice. The IC consumes 1 W from 1.0-V and 2.5-V supplies.