Design space exploration of RTL datapaths using Rent parameter based stochastic wirelength estimation

摘要

We present an assessment of a priori stochastic wire-length estimation as a viable technique for evaluating the interconnect requirements of designs explored in RTL datapath synthesis. The model estimates the wirelength requirements of a gate level netlist a priori, based on Rentian parameters extracted dynamically from RTL netlists. Experimental results indicate that the wirelength estimates of our dynamic Rent parameter extraction method are in agreement within an average of 3.96% to those obtained from designs synthesized by a commercial place-and-route tool, while offering an average speedup of 278% over physical synthesis, suggesting that stochastic wirelength estimation methods are a viable approach to guide design space exploration in high-level synthesis