Post-layout gate sizing for interconnect delay and crosstalk noise optimization

摘要

In this paper, we develop a new post-layout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. We have modeled the problem of gate sizing as a normal form game and solved using the Nash equilibrium. The noise induced on a net depends on the size of the gates driving the coupled nets and itself. Increasing the gate size of the driver increases the noise induced by the net on its coupled nets, where as, increasing the size of the driver of coupled nets increases the noise induced on the net itself, resulting in a conflicting situation. The problem of post-layout gate size optimization is difficult to solve due to its conflicting nature (M. R. Becer, 2003). Game theory provides a natural framework for handling such conflicting situations and allows multi-metric optimization. We have exploited this property of game theory to solve the cyclic dependency of crosstalk noise on its gate sizes, while modeling the problem of gate sizing for simultaneous optimization of interconnect delay and crosstalk noise, which again are conflicting in nature. Experimental results on several medium and large opencore designs indicate average improvements of 13.33% and 16.61% for interconnect delay and crosstalk noise, without any area overhead or need for re-routing