As memory market enters the Gigabit and GHz range with consumers demanding ever higher performance and diversified applications, new types of devices are being developed in order to keep up with the scaling requirements for cost reduction. Among these devices are well-known ones such as the recessed channel transistors, but also FinFET and vertically stacked transistors for DRAM and charge trap devices for Flash memory. The latter ones are still not at a manufacturable stage yet. Even more exotic memories implement new materials and stacked architectures on the cell, chip and package level. On the performance side, increasing speeds require higher time resolutions. The future difficulties of process control by far exceed those of conventional planar devices. Therefore device characteristics are expected to show ever increasing PVT variations. As these variations become more and more inevitable, especially as dimensions approach the atomic scale, negative effects on circuit and device performances have to be prevented by new, appropriate methods of 3D device modeling and circuit design which consider the mentioned parameter variations. In this talk such challenges will be discussed as well as some approaches to overcome them. An outlook will also be given about the memory technology trends in the next decades.
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