Reduction of the TSOP Warpage for Avoiding SMT Assembly Yield Degradation

摘要

It was noticed that the warpage of TSOP (Thin Small Outline Package) type memory package became larger than an acceptable level, what would cause yield reduction in an SMT (Surface Mount Technology) assembly line for the fabrication of memory modules. It was found that the transfer molding process, one of the memory IC packaging processes, was the cause of the package warpage. GR&R (Gage Reliability and Reproducibility) study was carried out in order to establish a method for measuring the package warpage. Then, a full factorial DOE (Design of Experiment) was carried out and the chase temperature was found to be the most critical process variable. Adjusting the chase temperature, the package warpage was reduced by 27%, from 0.104±0.012 mm to 0.076±0.008 mm.