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Addressing mode driven low power data caches for embedded processors

机译:寻址模式驱动的嵌入式处理器低功耗数据高速缓存

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The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs and cellular handsets, decreasing power consumption while increasing performance is desirable. Contemporary caches typically exploit locality in memory access patterns but do not exploit locality information encoded in addressing modes used to access memory. We present two schemes that use locality information inherent in memory addressing modes to reduce power consumption of cache or SRAM nearest to the processor. The level-0 data buffer scheme introduces a set of data buffers controlled by the addressing mode to eliminate over a third of all reads to the next level of memory (cache or SRAM). These buffers can also reduce load-use penalty in processors with long load pipelines. The address register tag-buffer scheme exploits the addressing mode to reduce tag array look-up in set associative first-level caches.
机译:嵌入式处理器的一级缓存和SRAM的大小和速度不断增长,以响应对更高性能的需求。在诸如PDA和蜂窝手持机之类的对功率敏感的设备中,希望在提高性能的同时降低功耗。当代的高速缓存通常利用存储器访问模式中的局部性,但是不利用以用于访问存储器的寻址模式编码的局部性信息。我们提出了两种方案,它们使用内存寻址模式中固有的位置信息来减少最接近处理器的缓存或SRAM的功耗。 0级数据缓冲区方案引入了一组由寻址模式控制的数据缓冲区,以消除对下一级内存(高速缓存或SRAM)的所有读取的三分之一。这些缓冲区还可以减少具有长负载管线的处理器中的负载使用损失。地址寄存器标签缓冲区方案利用寻址模式来减少在集合关联的一级缓存中查找标签阵列。

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