PERFORMANCE ANALYSIS OF DIFFERENT MULTIPLICATION STRATEGIES IN RECONFIGURABLE HARDWARE

摘要

A multiplier is one of the key hardware blocks in mostrnhigh performance systems such as FIR filters and DSP’s.rnThe performance of these systems is significantlyrninfluenced by the speed of the multipliers they utilise. Anrnapplication may need different optimized hardware (eitherrnfor power or for speed) at different time. A reconfigurablernplatform can accommodate such requirements. This paperrncompares two broad schemes of combinatorial multipliersrnimplemented using adders in reconfigurable hardware.rnFurthermore, the paper looks into applying the abovernmentioned strategies in two different platforms torncompare the variations in power, area and speed. Thernmultiplier implemented with carry save adder in parallelrnshowed better performance than the others. At minimum,rnthe above configuration shows 13% delay improvementrnas well as 18% power efficiency than the otherrnmultipliers. However, this gain is achieved at an expensernof 13% more hardware. All simulations are carried out onrna Xilinx Spartan 3E and Altera’s EP2S15F484C3 FPGArnusing VHDL.