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机译:用于多项式矩阵乘法的新型可重构硬件体系结构
Dept. of Electr. & Electron. Eng., Eur. Univ. of Lefke, Gemikonagi, Turkey;
array signal processing; convolution; decorrelation; field programmable gate arrays; polynomial matrices; vectors; PMM; Xilinx system generator tool; algorithmic accuracy; decorrelation; fast convolution technique; field-programmable gate array architecture; in-the-loop hardware cosimulations; multiple-input multiple-output systems; partly systolic FPGA architecture; polynomial matrix multiplications; polynomial vectors; reconfigurable hardware architecture; sensor array signal processing; Arrays; Convolution; Field programmable gate arrays; Hardware; MIMO; Polynomials; Field-programmable gate array (FPGA); SBR2P; Xilinx system generator for digital signal processor (DSP) tool; Xilinx system generator for digital signal processor (DSP) tool.; polynomial matrix computations; polynomial matrix multiplication (PMM);
机译:用于GF(2〜m)乘法的新硬件体系结构以及与椭圆曲线密码术的正态和多项式基乘的比较
机译:基于FPGA的硬件矩阵反转架构使用混合分段多项式近似收缩细胞
机译:可重新配置的内部产品硬件体系结构,以提高SDR系统中的硬件利用率
机译:多项式矩阵/向量乘法的新型可重构硬件实现
机译:可重构多项式基础架构,可在Galois字段中进行乘法运算
机译:可重配置硬件中的峰值排序的高效架构
机译:稀疏Laurent多项式与poisson序列的乘法 现代硬件架构