Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation

摘要

This paper describes a comparison of two Montgomerymodular multiplication architectures: a systolic and amultiplexed. Both implementations target FPGA devices. Themodular multiplication is employed in modular exponentiationprocesses, which are the most important operations of somepublic-key cryptographic algorithms, including the most popularof them, the RSA. The proposed systolic architecture presentsa high-radix implementation with a one-dimensional array ofProcessing Elements. The multiplexed implementation is a newalternative and is composed of multiplier blocks in parallelwith the new simplified Processing Elements, and it provides apipelined operation mode. We compare thetime×areaefficiencyfor both architectures as well as an RSA application. The systolicimplementation can run the 1024 bits RSA decryption processin just 3.23 ms, and the multiplexed architecture executes thesame operation in 4.36 ms, but the second approach saves up to28% of logical resources. These results are competitive with thestate-of-the-art performance.