10 Gb/s Single-chip data regeneration with an injection synchronised ring oscillator and an automatic phase adjustment

摘要

A new concept of high-speed data regeneration was developed by using an injection-synchronised narrowband ring oscillator for the clock recovery and an automatic phase adjusting loop for the optimum data decision. A single-chip data regeneration IC has been realised by using our 0.3#mu#m gate-length QW-HEMT GaAs technology and characterised on-wafer at STM-64 level (approx 10 Gb/s) of the SDH-standard.