Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, 1015 Lausanne, Switzerland;
Department of Electrical and Computer Engineering Lebanese American University, Byblos, Lebanon;
Department of Computer Science and Engineering University of California Riverside, 900 University Ave., Riverside CA92521, U.S.A.;
Ecole Polytechnique Federale de Lausanne (EPFL) School of Computer and Communication Sciences, 1015 Lausanne, Switzerland;
FPGA; logic chain; routing wire; dedicated connection; generic synthesis;
机译:利用多位连接来提高单向路由资源的区域效率,以便在FPGA上路由多位信号
机译:Metro-on-FPGA:一种可行的解决方案,可改善未来FPGA中的拥塞和路由资源管理
机译:深入了解Xilinx Virtex和Spartan系列FPGA的通用互连资源模型
机译:用通用逻辑链减少FPGA路由资源的压力
机译:通过增量逻辑重新合成和基于快捷方式的路由架构来改进FPGA设计。
机译:简短多方面的通用干预措施以改善血压控制和减少差异收效甚微
机译:面向数据路径的粗粒度逻辑和FpGa路由的体系结构
机译:具有异构资源的FpGa多资源感知分区算法