ASIC Physical Design Flow: Power Saving Opportunities on Interconnection Components

摘要

The ever-increasing density of SoC (System on Chip) has made their power consumption an issue in their own right. We present a specific power reduction technique at physical design stage of the digital design SoC conception flow: Capacitance-Toggle rate weighting which aims at reducing the switching power of the interconnection inside the Integrated Circuit. We implemented the technique and obtained experimental results on designs done on 28 nm technology node. The new placement power aware performs an improvement on average 12% in interconnection power and a 4% average in the total power. This method has been inducting into a Place and Route EDA (Electronic Design Automation) tool.