Hardware implementation of adaptive motion estimation and compensation for H.264/AVC

摘要

This paper describes the hardware architecture of the motion estimation and compensation module used in the H.264/AVC encoder. The architecture calculates simultaneously residuals and finds the best motion vectors with the quarter-pel accuracy. Checked motion vectors are generated using the algorithm able to fast achieve the best matching based on the adaptive techniques. The module is verified in the hardware encoder framework. The synthesis results and the real-time verification show that the design can work at 100 MHz and 200 MHz for FPGA Aria II GX devices and 0.13μm TSMC technology, respectively.