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Design and applications of a family of optoelectronic photocurrent logical elements on the basis of current mirror and comparators

机译:基于电流镜和比较器的一系列光电光电流逻辑元件的设计和应用

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We consider design of hardware realizations of optoelectronic logical elements of two-valued logic with current inputs and current outputs on the basis of CMOS current mirrors and circuits which realize the limited difference functions. We show advantages of such elements consisting in encoding of Boolean variables by the photocurrent levels, that allows easily to provide optical inputs (by photodetectors) and optical outputs (by light-emitting devices). The conception of construction of the family of the offered optoelectronic photocurrent logical elements (OPLE) consists in the use of a few current mirrors realized on 1.5 μm technology CMOS transistors. Presence of four - ten transistors, one - two photodetectors makes the offered circuits quite compact and allows their integration in 1D and 2D arrays. In the presentation we consider the whole family of the offered circuits, show the simulation results and possible prospects of application of the circuits in particular for time-pulse coding for multivalued, continuous, neuro-fuzzy and matrix logics. The simulation results of the NOT, AND, OR, OR-NOT current logical elements on the 1.5 μm technology CMOS transistors showed that the level of logical unit can change from 1 uA to 10 uA for low-power consumption variants and from 10uA to 100uA for high-speed variants. Signals delays, values of fronts and cutoffs at operation with impulse logical signals with 1uA logical unit are not exceed 70-140ns and at operation with impulse logical signals with 100uA logical unit are no more than 4-6ns and the consumption power is 200-400uW.
机译:我们考虑基于实现有限差分功能的CMOS电流镜和电路,设计具有电流输入和电流输出的二值逻辑光电逻辑元件的硬件实现。我们展示了这样的元件的优点,即通过光电流水平对布尔变量进行编码,可以轻松地提供光输入(通过光电探测器)和光输出(通过发光设备)。所提供的光电光电流逻辑元件(OPLE)系列的构造概念在于使用几个在1.5μm技术CMOS晶体管上实现的电流镜。四到十个晶体管,一到两个光电检测器的存在使所提供的电路非常紧凑,并允许它们集成在一维和二维阵列中。在演示中,我们考虑了所提供电路的整个系列,展示了仿真结果以及该电路的应用前景,特别是对于多值,连续,神经模糊和矩阵逻辑的时间脉冲编码。 1.5μm技术CMOS晶体管上NOT,AND,OR,OR-NOT电流逻辑元件的仿真结果表明,对于低功耗型号,逻辑单元的电平可以从1 uA变为10 uA,从10uA变为100uA用于高速变体。使用1uA逻辑单元的脉冲逻辑信号时的信号延迟,前沿和截止值不超过70-140ns,使用100uA逻辑单元的脉冲逻辑信号时的信号延迟,不超过4-6ns,功耗为200-400uW 。

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