Analytical and experimental assessment of the thermal peformance of surface mount packages

摘要

The junction-to-case and junction-to-ambient thermal resistances of ball grid array and peripheral array surface mount microelectronics packages were experimentally determined using an industry standard procedure. The effects of internal design variables such as the presence of metallic ground planes, number of wire bonds, use of underfill material and variations in the thermal properties were evaluated under natural convection conditions. The thermal performance of these same microelectronics packages was predicted with a simplified one-dimensional heat transfer model. The steady state temperature distribution and thermal resistances of two package designs were predicted with the computer model, and the thermal resistances were compared to the measured values. As part of the development of the analytical thermal model, a procedure is proposed to calculate the heat spreading resistances when orthotropic materials of different sizes are joined together. The one-dimensional model predicted the junction-to-ambient thermal resistances of the peripheral array packages to within approximately 8 percent of the measured results. The difference between the model predictions and the experimental results for the ball grid array designs was about 30 percent for thermally enhanced packages and less than 2 percent for the nonenhanced packages. Given the errors associated with an attempt to predict a three-dimensional heat transfer phenomenon with a one-dimensional program, the predictions of the simplified model were reasonably accurate. The one-dimensional model is an excellent first-cut design tool and can be used to give a simple evaluation of the themal performance of microelectronics packages. The one-dimensional model requires less computational effort, less input information, and less operator experience than a more complex heat transfer model such as a finite element analysis.