Simulation of spacer-based SADP (Self-Aligned Double Patterning) for 15nm half pitch

摘要

Spacer based SADP (Self-Aligned Double Patterning) is used increasingly in IC manufacturing as design rules outstrip the resolution capabilities of traditional single exposure lithography processes. In this paper, a 15nm half pitch SADP process based upon an EUV single exposure produced mandrel is modeled using commercial simulation software (PROLITH X4.2, KLA-Tencor corp.). Good accuracy is observed when the simulated results are compared to actual experimental results. Artifacts present in the final spacer pattern are clearly traceable to the resist imaging step.