On the phase noise of ΔΣ frequency discriminator for applications in frequency synthesizer

摘要

Phase noise analysis for the ΔΣ frequency discriminator is presented in this paper, and a new architecture is proposed to improve the noise performance. This technique uses a mixer following the VCO to downconvert discriminator input from RF range to IF. It reduces the effect of N times in-band phase noise amplification, and relaxes the requirement of timing accuracy in a higher order ΔΣ frequency discriminator. MATLAB simulation shows significant noise improvement in the presence of timing errors from logic devices.