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Adaptive Line Size Cache for Irregular References on Cell Multicore Processor

机译:单元多核处理器上不规则引用的自适应行大小缓存

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Software cache promises to achieve programmability on Cell processor. However, irregular references couldn't achieve a considerable performance improvement since the cache line is always set to a specific size. In this paper, we propose an adaptive cache line prefetching strategy which continuously adjusts cache line size during application execution. Therefore, the transferred data is decreased significantly. Moreover, a corresponding software cache -adaptive line size cache is designed. It introduces a hybrid Tag Entry Arrays, with each mapping to a different line size. It's a hierarchical design in that the misshandler is not invoked immediately when an address is a miss in the short line Tag Entry Array. Instead, the long line Tag Entry Array is checked first, which significantly increases the hit rate. Evaluations indicate that improvement due to the adaptive cache line strategy translates into 3.29 to 5.73 speedups compared to the traditional software cache approach.
机译:软件缓存有望在Cell处理器上实现可编程性。但是,由于高速缓存行始终设置为特定大小,因此不规则引用无法实现显着的性能改进。在本文中,我们提出了一种自适应的缓存行预取策略,该策略在应用程序执行期间不断调整缓存行的大小。因此,传输的数据大大减少。此外,设计了相应的软件高速缓存自适应行大小高速缓存。它引入了一个混合的Tag Entry Arrays,每个映射到一个不同的行大小。这是一种分层设计,当短线标签条目数组中的地址未命中时,不会立即调用未命中处理程序。取而代之的是,先检查长行的“标记条目数组”,这会大大提高命中率。评估表明,与传统的软件缓存方法相比,由于自适应缓存行策略的改进,转换速度提高了3.29至5.73。

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