Photonic VLSI for On-Chip Computing Architectures

摘要

In this paper, we demonstrate the feasibility of using on-chip optoelectronics within VLSI systems to address a wide range of signal distribution issues by examining the following fundamental question: how can we transmit information from one source to many destinations while minimizing propagation delay, skew, jitter, and noise in a way that is compatible with low-cost manufacturing and CMOS circuits? Example systems with such information distribution requirements include banked arrayable memories such as a DRAM or a dense imager with scanned high speed readout, or a clock distribution system. In all instances individual lines are typically connected to thousands of gates, slowing cell access times and generating skew. We demonstrate how the use of on-chip photonics within VLSI systems can reduce delays introduced by electrical wires in system-on-a-chip interconnects, busses, caches, and control lines at distances shorter than one meter and as short as a few millimeters. We also describe and demonstrate how a simple on-chip optoelectronic system addressing these problems can be realized at low cost, with monolithic photodetectors and on-chip waveguides in a commercial CMOS process, benefiting both ultra-short and one meter link architectures. This unexplored signal distribution architecture promises high optical to electrical efficiency, low noise, and the benefits of monolithic photodetection not previously achieved in existing approaches.