A W-band divider-less cascading frequency synthesizer with push-push ×4 frequency multiplier and sampling PLL in 65nm CMOS

摘要

A fully integrated 79-to-87GHz cascading frequency synthesizer, which combines a W-band push-push ×4 frequency multiplier and a K-band divider-less fundamental PLL with sampling phase detector, is implemented in a standard 65nm CMOS process. It consumes low power of 54mW, achieves as low as −100.1dBc/Hz @ 100kHz and −106.2dBc/Hz @ 1MHz phase noise performance at divide-by-2 frequency, covers 9.6% tuning range from 79 to 87GHz, and occupies smaller than 1.48×0.8 mm² silicon area. This frequency synthesizer is qualified to support 81-to-86GHz point-to-point high speed data link.