PLL PLL frequency synthesizer for diving the frequency in advance before multiplying of frequency and pre-scaler used whereto

摘要

The PLL frequency synthesizer, which divides the frequency before expansion, and the non-integer spare divider applied to it are posted. The PLL frequency synthesizer of the present invention includes an oscillation clock signal generator, a non-integer preliminary divider, a programmable divider and a frequency expander.;The oscillation clock signal generator receives the loop clock signal FV and generates an oscillation clock signal CLK that oscillates at a constant ratio with respect to the reference clock signal FR having a predetermined frequency. The non-integer preliminary divider divides the frequency f of the oscillation clock signal CLK by the division ratio of P / J to generate the preliminary signal XPRE. A programmable divider generates the loop clock signal FV by 1 / N (where N is an integer) of the frequency of the preliminary signal.;The frequency expander extends the frequency of the oscillation clock signal CLK to generate the frequency synthesized signal FO.