Mobility Enhancement of Peripheral PMOSFET Using e-SiGe Source and Drain in Sub-50nm DRAM

摘要

The mobility enhanced pMOS transistors have been successfully implemented into sub-50nm DRAM for the first time. The uni-axial strained channels were embodied by filling the recessed source / drain with epitaxial SiGe film. Mobility boosting and reduced external resistance enabled pMOS transistors to increase saturation current by 20%, and retarded boron diffusion reduced DIBL by 17mV/V compared to control process without degradation of DRAM cell data retention time characteristics. The local variation of threshold voltage is suppressed to the same level of control process. The hot electron induced punch-through (HEIP) degradation can be controlled to negligible degree.