首页> 外文会议>International Electron Devices Meeting >A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration
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A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (Φ-Flash), suitable for full 3D integration

机译:堆叠的SONOS技术,最多4个级别和6nm晶体纳米线,带有门 - 全息或独立的门(φ-Flash),适用于完整的3D集成

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We present the first experimental study of a Gate-All-Around (GAA) SONOS memory architecture with 4-level crystalline nanowire channels (down to 6nm-diameter). The technology is also extended to an independent double gate memory architecture, called Φ-Flash. The experimental results with 6nm nanowires show high programming windows (up to 7.4V), making the structure compatible with multilevel operation. Excellent retention even after 10~4 cycles is achieved. The independent double gate option has otherwise been successfully integrated with 4-level stacked nanowires for multibit applications. The Φ-Flash exhibits up to 1.8V ΔV_(Th) between its two gates, demonstrating multibits operation. The basic process to fully disconnect the different nanowires in view of a full 3D integration of a memory array is discussed.
机译:我们介绍了具有4级晶体纳米线通道(低至6nm)的门 - 全部(GaA)Sonos内存架构的第一个实验研究。该技术还扩展到独立的双栅极内存架构,称为φ-Flash。具有6nm纳米线的实验结果显示出高编程窗口(高达7.4V),使结构与多级操作兼容。即使在10〜4个循环中也是优异的保留。否则,独立的双栅极选项已经成功集成了4级堆叠纳米线,用于多BiBIT应用。 φ-Flash在其两个门之间显示出高达1.8VΔV_(TH),证明了多利益操作。讨论了鉴于完全3D集成存储器阵列的完全纳米线的基本过程。

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