It is noted that, to test wiring interconnects in a printed circuit board, especially one equipped with boundary-scan devices, it is important to minimize the test size while maintaining diagnostic capability. This has provided the motivation for research work that explores efficient test generation and diagnosis algorithms. The authors propose a unified theory for designing various types of interconnect test algorithms. They demonstrate that the algorithms proposed in the literature are special cases of the general algorithms given in the present work. The new algorithms are shown to be optimal or near optimal for a given set of design and process parameters. They increase the designer's flexibility by offering a full range of solutions (i.e., test vector sets) based on various tradeoff criteria, such as test compactness and diagnostic accuracy. Parameters for quantifying the quality of the tests are described. The significance and limitations of the proposed algorithms are also discussed.
展开▼
