53Gbps Native GF(2~4)~2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45nm High-Performance Microprocessors

摘要

An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for contentprotection in high-performance microprocessors. Compared to conventional AES implementations, this design computes the: entire AES round in native GF(2~4)~2 composite-field with one-time GF(2~8)-to-GF(2~4)~2 mapping cost amortized over multiple AES iterations. This approach along with a fused Mix/InvMixColumns circuit and folded ShiftRow datapath. results in 20% area savings and 67% reduction in worst-case interconnect length, enabling AES-128/192/256 ECB block throughput of 53/44/38Gbps, 125mW power measured at 1.I V; 50°C.