53 Gbps Native Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors

摘要

This paper describes an on-die, reconfigurable AES encrypt/decrypt hardware accelerator fabricated in 45 nm CMOS, targeted for content-protection in high-performance microprocessors. 100% round computation in native ${rm GF}(2 ^{4} ) ^{2}$ composite-field arithmetic, unified reconfigurable datapath for encrypt/decrypt, optimized ground & composite-field polynomials, integrated affine/bypass multiplexer circuits, fused Mix/InvMixColumn circuits and a folded ShiftRow datapath enable peak 2.2 Tbps/Watt AES-128 energy efficiency with a dense 2-round layout occupying 0.052 ${hbox {mm}}^{2}$ , while achieving: (i) 53/44/38 Gbps AES-128/192/256 performance, 125 mW, measured at 1.1 V, 50$,^{circ}{hbox{C}}$ , (ii) scalable AES-128 performance up to 66 Gbps, measured at 1.35 V, 50$,^{circ}{hbox{C}}$ , (iii) wide operating supply voltage range with robust subthreshold voltage performance of 800 Mbps, 409 $mu{hbox {W}}$, measured at 320 mV, 50 $,^{circ}{hbox{C}}$ (iv) 37% Sbox delay reduction and 25% area reduction with a compact Sbox layout occupying 759 $mu{hbox {m}} ^{2}$ (v) 67% reduction in worst-case interconnect length and 33% reduction in ShiftRow wiring tracks and (vi) 43% reduction in Mix/InvMixColumn area with no performance penalty.