A 54 Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS

摘要

A low clock power, static, fully-interruptible, single-phase-clocked, shared-keeper flip-flop without local clock inverters and no write-back failure reduces the clock transistor count to 6 instead of 12 in conventional transmission-gate flip-flop, achieving 54^{% reduction in total cell level power and 100mV improved VMIN. An experimental microcontroller with shared-keeper sequentials, fabricated in 14nm CMOS, shows 6.5% lower measured chip level power at iso-frequency compared to the previously published single-phase-clocked AOI sequentials at 0.75V, 25°C.}