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Off-line mask-to-mask registration characterization as enabler for computational overlay

机译:离线屏蔽到掩码注册表征作为计算叠加的启动器

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After the introduction of multi-patterning techniques like multiple Litho-Etch (LE~n) steps and/or Spacer Assisted Double/Quadruple Patterning (SADP/SAQP), the amount of masks required to produce a semiconductor device has increased significantly. The main reason was that a functional layer could no longer be exposed in one single litho step due to the elevated pitch requirements. Consequently, the required pattern had to be split-up and divided over multiple masks. One can imagine that this has put a huge constraint on the mask-to-mask on-product overlay requirements and control. It was already shown before that for the LE2 use-case the mask-to-mask contribution is the second largest contributor (after the scanner) to the overall on-product overlay. In order to keep the on-product overlay within specification over time, the number of on-wafer overlay metrology steps inside the fab increased even more. Since more masks are used per layer, multiple combinations are now possible to measure and control both the intra-layer as well as the inter-layer overlay. As a consequence, the increasing number of metrology steps has resulted in a negative impact on the overall wafer/lot cycle time in the fab. It would be beneficial to fully characterize the mask-to-mask overlay off-line and apply computational overlay techniques to compute the on-wafer overlay. This enables smart metrology sampling to address and reduce the overall wafer/lot cycle time inside the fab. In this work, we performed a correlation study between off-line mask-to-mask registration metrology and on-wafer measurements. The off-line overlay measurements were performed on a PROVE? tool while the exposures and scanner readouts were executed on an ASML TWINSCAN?. Two ASML qualification (BaseLiner) masks were used for this purpose. Extensive off-line registration measurements were performed on both reticles including the reticle alignment marks as well as the image field metrology features (gratings). We show an excellent correlation between the measurements on the PROVE? tool and the on-wafer results reaching R2 > 0.96 with an accuracy of 0.58-nm. The accuracy is determined by the reticle alignment accuracy on the scanner and the quality of the masks. We have identified the underlying contributors to the error budget to enable a further improvement of the correlation between the mask-to-mask and the on-wafer overlay. Since the results of this first investigation were so promising, the effect of a pellicle mounted on one of the masks was studied as well. The off-line mask-to-mask registration metrology was repeated and the resulting computational overlay has been compared with the on-wafer results.
机译:在介绍多图案化技术之后,如多个蚀刻(LE〜N)步骤和/或间隔辅助双/四倍图案化(SADP / SAQP),产生半导体器件所需的掩模量显着增加。主要原因是由于升高的俯仰要求,功能层不能再暴露在一个单一的Litho步骤中。因此,必须在多个掩模上分开并划分所需的图案。人们可以想象,这对掩模到掩模的产品覆盖要求和控制已经对巨大的限制。它已经显示在其中,在LE2用例之前,掩码到掩码贡献是第二大贡献者(扫描仪之后)到整个产品上叠加。为了随着时间的推移保持在规范内的上产品覆盖,晶圆厂内的晶片内覆盖度量的数量增加更多。由于每个层使用更多掩模,因此现在可以进行多种组合来测量和控制帧内层以及层间覆盖层。结果,越来越多的计量步骤导致对Fab中的整体晶片/批次循环时间产生负面影响。完全表征掩模到掩模覆盖离线并应用计算覆盖技术将是有益的,以计算晶片覆盖物。这使得智能计量采样采样以解决并减少工厂内的整体晶圆/批次周期时间。在这项工作中,我们在离线掩模到掩模登记计量和晶片上进行了相关研究。在证明时执行离线覆盖测​​量值?工具在ASML TWINSCAN上执行曝光和扫描仪读数时,为此目的使用了两个ASML资格(Baseliner)面具。在包括掩模版对准标记的两个掩模上进行广泛的离线注册测量以及图像场测量特征(光栅)。我们在证明的测量之间显示出优异的相关性?工具和晶圆圈结果达到R2> 0.96,精度为0.58纳米。精度由扫描仪上的掩模版对准精度和掩模的质量决定。我们已经将基础贡献者识别出错误预算,以进一步改进掩模到掩模和晶片上覆盖之间的相关性。由于这一首次调查的结果如此希望,因此还研究了安装在其中一种面罩上的薄膜的效果。重复离线掩模到掩模注册测量,并将得到的计算覆盖层与晶片上的导向结果进行了比较。

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