Novel integration technology with capacitor over metal (COM) by using self-aligned dual damascene (SADD) process for 0.15 μm stand-alone and embedded DRAMs

摘要

A novel integration technology with capacitor over metal(COM) for 0.15μm stand-alone and embedded DRAMs is developed by using self-aligned dual damascene(SADD) process, which offers great breakthroughs. First, many issues of back-endmetallization encountered in conventional COB(capacitor over bit line) DRAMs are simply overcome because capacitor is formed after metal line. Second, memory cell capacitor can be integrated much simply and easily compared to that of conventional COBbecause memory cell contact and storage node is simultaneously formed. Furthermore, transistor performance can be greatly improved because novel poly Si/Al{sub}2O{sub}3/poly-Si capacitor is integrated below 400°C.