首页> 外国专利> Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM

Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAM

机译:位线互连方案,用于消除独立或嵌入式DRAM中具有位线下电容器的堆栈DRAM单元中的耦合噪声

摘要

A method for forming a stack DRAM cell with CUB wherein coupling noise is eliminated is described. Bit-lines are formed according to one of three methods. In a first method, a first pair of bit-lines is fabricated in a first metal layer and a second pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein the first pair of bit-lines is horizontally spaced from the second pair of bit-lines. In a second method, a first of each pair of bit-lines is fabricated in a first metal layer and a second of each pair of bit-lines is fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein the first of each pair of bit-lines is horizontally spaced from the second of each pair of bit-lines. In a third method, each bit-line is divided into segments. First segments of a bit-line are fabricated in a first metal layer and alternating segments of the bit-line are fabricated in a second metal layer separated from the first metal layer by an insulating layer wherein for each pair of bit-lines, facing segments of a first and second of the bit-line pair are fabricated in different metal layers wherein the first of each pair of bit-lines is horizontally spaced from the second of each pair of bit-lines.
机译:描述了一种用于形成具有CUB的堆叠DRAM单元的方法,其中消除了耦合噪声。根据三种方法之一形成位线。在第一种方法中,第一对位线制造在第一金属层中,第二对位线制造在第二金属层中,第二金属层通过绝缘层与第一金属层分开,其中第一对位线-线与第二对位线水平间隔。在第二种方法中,每对位线中的第一对在第一金属层中制造,而每对位线中的第二对在第二金属层中通过绝缘层与第一金属层隔开,其中每对位线中的第一条与每对位线中的第二条水平地间隔开。在第三种方法中,每条位线被分成段。位线的第一段被制造在第一金属层中,位线的交替段被形成在通过绝缘层与第一金属层隔开的第二金属层中,其中对于每对位线,面对的段在不同的金属层中制造第一和第二位线对中的第一和第二位线,其中每对位线中的第一与第二对位线中的第二水平地间隔开。

著录项

  • 公开/公告号US6500706B1

    专利类型

  • 公开/公告日2002-12-31

    原文格式PDF

  • 申请/专利权人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY;

    申请/专利号US20010809834

  • 发明设计人 MIN-HWA CHI;

    申请日2001-03-19

  • 分类号H01L218/242;

  • 国家 US

  • 入库时间 2022-08-22 00:05:04

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