Device scaling in CMOS technology has approached to 10nm range and below. The gate dielectric, being the critical constraint, has evolved significantly and requires constant quality improvements in order to keep the proper functioning of the transistors and memory devices. While the transistor has transformed from a planar device to a three-dimensional device to a gate all around device, several new devices such as ferroelectric FETs and negative capacitance FETs have emerged to be integrated into standard CMOS technology. Additionally, many forms of memory devices such as resistive random-access memory (ReRAM) devices and ferroelectric RAM devices are being investigated for possible implementation of artificial intelligence hardware. All these devices use high dielectric constant (high-k) materials in some form or other. The electrical performance in these devices depends on the dielectric deposition process, precise selection of deposition parameters, pre-deposition surface treatments and subsequent thermal budget. In this work we describe the evolution of dielectric science in nanoelectronics.
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