14 nm FinFET Stress Engineering with Epitaxial SiGe Source/Drain

摘要

The SiGe source/drain is going to be the main stress source for the 14 nm PMOS FinFET due to the tight gate pitch and due to the gate-last high-k metal gate (HKMG). This paper explores key challenges of FinFET stress engineering that is based on the epitaxial SiGe S/D. These challenges are FinFET- specific and can be addressed by carefully balancing several design and process trade-offs simultaneously. An appropriate 3D modeling methodology is demonstrated to handle the new FinFET-specific design and process challenges.