Tensile Strained Ge Layers Obtained via a Si-CMOS Compatible Approach

摘要

Although rapid advances in Si photonics over the last decade has enabled mass production of higher functionality and lower cost photonic components (such as waveguides, couplers, modulators, photodetectors, etc..) integrated with both digital and analog circuitry in silicon complementary metal oxide semiconductor technology (Si-CMOS), an efficient electrically-pumped light emitter integrated in the Si-CMOS has so far been considered the Holy Grail of the monolithic electronics-photonics integration. Among the different pathways leading to the on-chip integration of the light source, epitaxial lasers on silicon comprising active regions based on III-V or SiGe heterostructures have been proposed [1]. In particular Ge heteroepitaxial layers on Si are very promising since key photonic components for this material system, including high speed detectors and modulators, have already been successfully integrated in standard CMOS process flow. As a matter of fact, Ge is now a "fab"-compatible material deposited by means of fully qualified production processes and it is now considered one of the most promising material for "more than Moore" device development [2]. An optically pumped Ge-on-Si laser demonstrating CW operation at room temperature, has already been fabricated [3]. To achieve this goal, the authors exploited the small residual tensile strain (~0.2%) accumulated during the growth process and n-type doping. Although optical gain values as high as 1000 cm-1 are expected in such a system, the maximum gain reported so far is 50 cm-1, owing to the difficulties to achieve the n-doping density requested (~1020 cm-3) because donor solubility, dopant activation, and material processing issues. Increasing the tensile strain in to the Ge layer would allow to increase net optical gain value using easier-to-achieve donor density. Fabrication approaches based either on micromechanical engineering [4-7] or on the use of a str- ssor layer [8] have been successfully proposed. However, none of these methods are viable for a "true" monolithic integration in a CMOS foundry owing to either materials [6,8] or micro-fabrication and processing issues [4,5,7]. Here we present a fabrication method allowing to achieve high values of tensile strain in Ge layer deposited on a SOI substrate to be used as active material in light emitting devices. The fabrication process of the investigated structures has been carried out on 8" wafer using standard qualified CMOS-lithography process. A Ge layer deposited on a SOI substrate by means of production-grade CVD reactor is covered by highly compressively strained SiN layer acting as a stressor. Upon appropriate lithography of the SiN/Ge/SOI stack, micro-stripe and suspended micro-bridges such the one displayed in Fig. 1 are obtained. The relaxation of the compressive strain stored in to the SIN layer induces a tensile strain in to the Ge active layer. Micro-structures having sizes in the 10 to 1000 μm2 range and different orientation have been investigated in order to investigate the strain relaxation process as a function of geometry. Finite element method simulation and micro-Raman spectroscopy have been used to measure the strain distribution in to the micro-structure: values as high as ~1 % have been obtained. Room temperature photoluminescence (PL) is observed from these structures, giving evidence for strong direct-band related emission at wavelengths corresponding to those expected for the PL emission from tensile strained Ge layers. Figure 2 shows an example of PL spectrum of a microstripe structure as shown in Figure 1 (a). The luminescence is red-shifted as compared to the blanket structure because of tensile strain. Fabry-Perot oscillations due to reflections along t