Impact of Strain Engineering on Nanoscale Ge PMOSFET

摘要

The stress distributions in strained Ge PMOSFETs with high-k dielectric layer, metal gate, and GeSn alloy S/D stressors were studied. It was found that the geometric effects, such as channel width and length, could impact the achievable transistor performance gains. The resulted mobility improvement was analyzed by Kubo-Greenwood formula. This work helps the future Ge-based CMOS device design and demonstrates that strain engineering is important for the future nanoscale device technology.