Trap-Assisted Tunneling in Vertical Si and SiGe Hetero-Tunnel-FETs

摘要

This paper reports on the integration of vertical Tunnel FETs (TFETs) with SiGe heterojunction and analyzes the presence of trap-assisted tunneling impacting the device behavior and degrading the onset characteristic. Temperature measurements are used to distinguish between band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT) mechanisms. TCAD simulations are in good agreement with experimental data, and suggest that boosting the BTBT component by further bandgap decrease (Ge) should be beneficial in lowering the impact of trap-assisted tunneling.