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Characterization of Electronic Charged States of Silicon Nanocrystals as a Floating Gate in MOS Structures

机译:硅纳米晶体电子带电状态的特征在MOS结构中的浮栅

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We have studied capacitance-voltage (C-V) and displacement current-voltage characteristics of MOS capacitors with Si nanocrystals embedded in the gate oxide as a floating gate in dark and under visible light illumination at room temperature to gain a better understanding of discrete charged states of the Si-dots floating gate. The Si-dots floating gate with a dot density of 2.8 x 10~(11) cm~(-2) and an average dot size of 8nm was fabricated on ~ 2.8nm-thick thermally-grown SiO_2 as a tunnel oxide by the thermal decomposition of SiH_4, and covered with 7.5nm-thick control oxide prepared by thermal oxidation of a-Si. C-V characteristics of Al-gate MOS capacitors on p-type and n-type Si(100) show unique hystereses due to the charging and discharging of the Si-dots floating gate with a symmetric pattern reflecting the Fermi level of the substrate, which enable us to rule out the contribution of traps with a specific energy state to the observed hystereses. For each of high-frequency C-V curves measured in dark, a single capacitance peak appears only around a flat-band voltage condition, which is attributed to the quick flat-band voltage shift caused by the collective emission of charges retaining in the Si-dots floating gate as confirmed from the corresponding displacement current peak. Under visible light illumination, another capacitance peak due to collective charge injection to the electrically neutral Si-dots floating gate becomes observable in the inversion condition governing the on-state of MOS FETs. Thus, the optimum bias conditions for dot-floating gate MOSFETs can be predicted from the capacitor characteristics measured under light illumination.
机译:我们已经研究了MOS电容器的电容电压(CV)和位移电流 - 电流 - 电压特性,其具有嵌入式氧化物中的Si纳米晶体作为漂浮栅极在室温下的漂浮栅极,以便更好地理解离散的指控状态Si-dots浮栅。漂浮栅极的漂浮栅极,具有2.8×10〜(11)cm〜(-2)的平均点尺寸和8nm的平均点尺寸,以〜2.8nm厚的热生长的siO_2制成作为热量的隧道氧化物SiH_4的分解,并用7.5nm厚的控制氧化物通过A-Si的热氧化制备。 P型和N型Si(100)上的Al栅极MOS电容器的CV特性显示了由于Si-Dots浮栅的充电和放电,具有反映基板的Fermi水平的对称图案的Si-Dots浮栅的充电和放电。我们要排除陷阱对观察到的歇斯底里的特定能量状态的贡献。对于在暗中测量的每个高频CV曲线,单个电容峰值仅出现在平坦带电压条件周围,这归因于由在Si-Dots中保留的电荷的集体发射引起的快速平带电压移位浮栅从相应的位移电流峰值确认。在可见光照明下,在控制MOS FET的导通状态的反转条件下,另一电容峰值由于与电中性Si点浮栅的集体电荷喷射而被观察到。因此,可以从光照射下测量的电容器特性预测点浮栅MOSFET的最佳偏置条件。

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