Predictions for the properties of integrated circuits and systems fabricated in emerging nano-technologies indicate a rising level of static and dynamic faults due to new fault mechanisms. Not only transient faults due to particle radiation are becoming a problem, but also wear-out effects on transistors and interconnects. While transient faults can be covered by well-known technologies such as error-correcting codes and triple modular redundancy, permanent faults essentially need a technology that provides built-in self repair (BISR). BISR is actually known and available for regular structures such as memory blocks, but is much more difficult to implement on irregular logic. The paper proposes a scheme for logic BISR, gives estimates for the associated overhead, and describes inherent limitations.
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