This work describes the development of an optimized partitioning algorithm for HW/SW Codesign, which employs more realistic cost measures than previous partitioning algorithms and takes into account FPGA reconfiguration time. This algorithm is then used to find the optimal implementation of a digital RAKE receiver for DS-CDMA on an heterogeneous (hardware/software) platform. We additionally describe a new architectural approach for this type of receiver: in contrast with conventional architectures, which suppose a constant number of demodulation forgers, our new architecture allows a dynamic number of fingers, one for each propagation environment. The introduced flexibility allows this RAKE receiver to have the required computational power for each possible environment. It constitutes the selected application to test our partitioning algorithm.
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