HW/SW design and realization of a size-reconfigurable DCT accelerator

摘要

In this paper a reconfigurable size MDCT accelerator is modeled and synthesized. Starting from the C code of the desired application that cannot run in real time on the given platform (a LEON processor) we isolate the computationally extensive modules of the MDCT to be implemented an accelerator. Because of similarities of their data flow grapes we modify the R2SDF architecture of the FFT and fit it to the MDCT algorithm it by adding modules to solve the irregularities in its data flow graphs. The resultant architecture is modular and size-reconfigurable.