An Efficient QCA Vedic Multiplier for Nanotechnology Applications

摘要

Quantum-dot cellular automata (QCA) is a resourceful nano grade estimation technique which recommend lesser proportion like low power consumption and less area related to CMOS designing procedure. Innovative digital automation always heading towards higher density, and very less power using up. One of the updated nanotechnologies utilized nowadays is QCA that is depends on the Coulomb repulsion. Derived computing could be an effective prototype for energy efficient layouts in nano-scale. A multiplier is a vital part of DSP (Digital Signal Processing) and many more digital circuits applications. We emphasize on QCA Vedic multiplier structures agreeing to Vedic science by old Indian figures. In this paper, we design an ultra efficient and, less complex Vedic $2imes 2$ and $4imes 4$ multipliers with the help of the proposed QCA XOR gate and less complex QCA half adder and proficient 4-bit new ripple carry adder using QCADesigner simulation environment for less energy and fast speed nanotechnology application. The simulation result illustrates the proposed design outrun as related to previously existing plans within the specification of cell estimations, an area and latency.