Transforming Ladder Logic to Verilog for FPGA Realization of Programmable Logic Controllers

摘要

Programmable Logic Controllers (PLCs) are used in many industrial settings to control and automate machinery in a manufacturing process. Typically, these devices are programmed in ladder logic, which is used to define the logical control of connected machines in parallel. The resulting system needs to control machines in the millisecond time domain, and therefore, PLCs can implement what appears to be millisecond parallel control by emulating the logic with GHz processing capabilities of modern processors. This system solution works, but PLCs are expensive and cannot support all design implementations, and our work begins to support a community examination to replace the control computation resources with FPGAs. The reason for this shift in technology is FPGAs are by nature parallel, programmable (reconfigurable), low cost, and have a high pin capacity, which makes them excellent substitutes for PLCs. To evaluate this, however, the first step is to build a tool that converts ladder logic to a format mappable to FPGAs. For this, we have created an open-source tool called, Hashigo, that converts ladder logic to synthesizable Verilog. In this work, the tool is used to convert a ladder logic design to Verilog that is then mapped to an FPGA, and we verify that the resulting FPGA control is equivalent to that of the same benchmark implemented on an existing commercial PLC. For the benefit of the community, this software is released to the community as open-source so that both academic and commercial possibilities in this technology can be further advanced.