A 2.4GHz Low-Power Subsampling/Sampling-Mixed Fractional-N All-Digital PLL

摘要

Phase-locked loops (PLL) are critical for frequency synthesisin modern wireless transceivers. In modernCMOS technology, all-digital PLLs engages more benefitsfrom the downscaling of transistors . SubsamplingPLLs can give a better trade-off between power and phasenoise but it may possibly unable to lock the output in thedesired frequency.In this work, a subsampling/sampling-mixed fractional-N all-digital PLL is proposed. To maintain a balance betweenpower and noise, an automated switch betweensubsampling mode and sampling mode is shown.