A Digital Circuit for Jitter Reduction of GPS-disciplined 1-pps Synchronization Signals

摘要

The Global Positioning System (GPS) satellites transfer accurate time from atomic clocks, thus enabling the receivers on Earth to produce high-stability synchronization signals (i.e., trains of low-jitter pulses without drift). The timing accuracy of the generated stream of pulses depends on the features as well as on the cost of the specific GPS receiver employed. This paper describes a fully digital synchronization circuit that is able to reduce the jitter associated to the 1 pulse per second (1-pps) signal generated by a typical low-cost receiver of moderate timing accuracy within a short settling time interval. The proposed circuit has been implemented using an FPGA and the jitter reduction has been estimated experimentally.