在Gardner定时同步方法中,当达到同步时,小数插值间隔uk 应该是一个固定值；但由于高斯噪声的影响,uk 会产生定时抖动,这会延长同步建立时间,进而提高误码率。基于此,提出了一种简单可实现的减小定时抖动的方法。具体是在定时同步检测前后分别增加预滤波器模块和系数值为1的环路系数模块。使用Simulink软件搭建仿真模型并对上述改进进行仿真验证,仿真结果表明,该方法能够减小定时抖动,降低误码率。%In the method of Gardner timing synchronization, when the system reaches synchronization, the fractional interpolation interval shall be a fixed value, however, because of the influence of Gaussian noise, uk may generate timing jitter, this will prolong the building period for synchronization and increase bit error rate. Thus the simple method for reducing timing jitter is proposed, that is:adding a pre-filtering module and a loop coefficient module with coefficient value 1, before and after the timing synchronization detection respectively. The simulation model is built by using Simulink software, and simulation verification for the improvement is conducted. The results of simulation show that this method can reduce timing jitter and bit error rate.
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