New Symmetric 9-Level Inverter Topology with Reduced Switch Count and Switching Pulse Generation Using Digital Logic Circuit

摘要

In this paper, a new symmetrical 9-level inverter topology with reduced number of switches is recommended. The proposed inverter uses four dc voltage sources and eight power switches to generate a 9-level voltage across the series RL load. The proposed inverter structure is compared with several other symmetrical topologies which indicate the reduction in the number of switches, total number of conducting switches and TSV value, which in turn, achieves higher inverter efficiency and lower switching losses. Finally, the inverter performance is analyzed by generating a 9-level output voltage using Matlab/Simulink.